The present invention relates to a program-verify circuit for an electrically re-writable memory cell which has a floating gate and a control gate and permits storage of a multi-valued (multi-bit or multilevel) data such as ternary or higher data, and a program-verify method using the above program-verify circuit.
In recent years, developments have been aggressively made on a memory cell having a floating gate and a control gate and being electrically re-writable. The above memory cell will be simply abbreviated as "memory cell" hereinafter. The memory cell is constituted of one memory element or composed of a plurality of memory elements depending upon types. As a technique for materializing a large capacity and a low cost of a memory cell, the technique of multi-bit (multilevel) storage for storing data of 2 bits or more, i.e., a ternary or multi-valued data in one memory element is attracting attention. In specific methods of multi-bit storage, which methods are applied to a memory element, various methods are proposed concerning data readout methods, program-verify methods (data writing methods), and so forth, depending upon differences in types such as a NOR type nonvolatile semiconductor memory cell (to be referred to as "NOR type memory cell" hereinafter), a NAND type nonvolatile semiconductor memory cell (to be referred to as "NAND type memory cell" hereinafter) and the like.
The performance method of a NOR type memory cell proposed by Intel Corp. will be outlined below. For details, see "NIKKEI MICRODEVICE", November issue of 1997, pages 126 to 130 (to be referred to as "Literature" hereinafter).
FIG. 4A shows the cell-array structure of the above NOR type memory cell. FIG. 4B shows a schematic partial cross-sectional view of a memory element constituting the NOR type memory cell. The structures of the cell-array and the memory element are the same as those of a conventional NOR type memory cell. In writing of data into the memory cell, when a positive high voltage is applied to a word line and a positive high voltage is applied to a bit line, hot electrons generated in a drain region of the memory element are injected into a floating gate (also called a floating electrode or a charge storage electrode) to set a threshold voltage V.sub.th of the memory element at a desired value. The value of the threshold voltage V.sub.th of the memory element, i.e., the injection amount of electrons into the floating gate is controlled by accurately controlling the voltage to be applied to a control gate (also called a control electrode) and the drain region. When data is erased, electrons are extracted from the floating gate to a source region by applying a high voltage to the source region, to set the threshold voltage V.sub.th of the memory element at a lowest voltage.
FIG. 5 schematically shows a distribution of the memory elements with regard to reference points (P.sub.0, P.sub.2, P.sub.3) and reference voltages (R.sub.1, R.sub.2, R.sub.3) when 2 bits are stored in one memory element. The threshold voltages V.sub.th of the memory elements storing data (1,1), (1,0), (0,1) and (0,0) and the reference voltages V.sub.R1, V.sub.R2 and V.sub.R3 have relationships as shown in the following Table 1.
TABLE 1 ______________________________________ Data (1,1) V.sub.th &lt;V.sub.R1 Data (1,0) V.sub.R1 &lt;V.sub.th &lt;V.sub.R3 Data (0,1) V.sub.R2 &lt;V.sub.th &lt;V.sub.R3 Data (0,0) V.sub.R3 /V.sub.th ______________________________________
In data readout performance, as schematically shown in FIG. 15, a current is flowed in a selected bit line, and the current flowing in the bit line is compared through three sensing amplifiers. A bias condition to the memory element is determined such that the current I.sub.cell flowing in the bit line is in proportion to the threshold voltage V.sub.th. Outputs from the three sensing amplifiers are inputted to a logic circuit, which converts the above outputs to two parallel outputs D.sub.0 and D.sub.1. When data stored in the memory element is (1,1), I.sub.R1ref &lt;I.sub.cell, and all the sensing amplifiers output "1", the logic circuit outputs "11". When data stored in the memory element is (1,0), I.sub.R2ref &lt;I.sub.cell &lt;I.sub.R1ref, and the sensing amplifier 1 outputs "0" and the sensing amplifiers 2 and 3 output "1", so that the logic circuit outputs "10". When data stored in the memory element is (0,1), I.sub.R3ref &lt;I.sub.cell &lt;I.sub.R2ref, the sensing amplifiers 1 and 2 output "0" and the sensing amplifier 3 outputs "1", so that the logic circuit outputs "01". When data stored in the memory element is (0,0), I.sub.cell &lt;I.sub.R3ref, all the sensing amplifiers output "0", so that the logic circuit outputs "00".
The program-verify is performed on a similar mechanism.
Several configuration examples of a multi-bit NAND type memory cell have been also reported. For example, as a method of reading multi-valued data, one example is a method in which a word line potential is changed to compare an output potential of a bit line with a reference potential, and another example is a method in which a potential level which appears in a bit line is directly read out when a predetermined potential is applied to a common source line while a word line potential is fixed. The latter method is disclosed, e.g., in JP-A-7-307091.
In the NOR type memory cell shown in the above Literature, multi-valued data can be converted to binary data at once, and there is an advantage that there is almost no difference in the readout rate in a multi-valued method and that in a binary method. However, as shown in FIG. 15, three sensing amplifiers are required per bit line, and further, a reference cell-array is also required, so that there are problems that a circuit configuration is complicated and that a layout area is increased. The nonvolatile semiconductor storage device disclosed in JP-A-7-307094 has similar problems that its circuit configuration is complicated and a layout area is increased.